1. Field of the Invention
The present invention generally relates to semiconductor memory devices, and more particularly, the present invention relates to the core layout of semiconductor memory devices.
A claim of priority is made to Korean Patent Application No. 10-2005-0024542, filed on Mar. 24, 2005, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
2. Description of the Related Art
A phase-change random access memory (PRAM), also known as an Ovonic Unified Memory (OUM), includes a phase-change material such as a chalcogenide alloy which is responsive to energy (e.g., thermal energy) so as to be stably transformed between crystalline and amorphous states. Such a PRAM is disclosed, for example, in U.S. Pat. Nos. 6,487,113 and 6,480,438.
The phase-change material of the PRAM exhibits a relatively low resistance in its crystalline state, and a relatively high resistance in its amorphous state. In conventional nomenclature, the low-resistance crystalline state is referred to as a ‘set’ state and is designated logic “0”, while the high-resistance amorphous state is referred to as a ‘reset’ state and is designated logic “1”.
The terms “crystalline” and “amorphous” are relative terms in the context of phase-change materials. That is, when a phase-change memory cell is said to be in its crystalline state, one skilled in the art will understand that the phase-change material of the cell has a more well-ordered crystalline structure when compared to its amorphous state. A phase-change memory cell in its crystalline state need not be fully crystalline, and a phase-change memory cell in its amorphous state need not be fully amorphous.
Generally, the phase-change material of a PRAM is reset to an amorphous state by joule heating of the material in excess of its melting point temperature for a relatively short period of time. On the other hand, the phase-change material is set to a crystalline state by heating the material below its melting point temperature for a longer period of time. In each case, the material is allowed to cool to its original temperature after the heat treatment. Generally, however, the cooling occurs much more rapidly when the phase-change material is reset to its amorphous state.
The speed and stability of the phase-change characteristics of the phase-change material are critical to the performance characteristics of the PRAM. As suggested above, chalcogenide alloys have been found to have suitable phase-change characteristics, and in particular, a compound including germanium (Ge), antimony (Sb) and tellurium (Te) (e.g., Ge2Sb2Te5 or GST) exhibits a stable and high speed transformation between amorphous and crystalline states.
FIG. 1 is an equivalent circuit diagram of an example of a phase change memory cell C of a diode type PRAM. In this example, the memory cell C includes a phase change resistance element GST and a diode D connected in series between a bit line BL and a word line WL. The phase change memory cell C is either selected or non-selected (e.g., for programming) depending on the voltage level of the word line WL. In particular, the memory cell C is selected by driving the word line WL to ground, whereas the memory cell C is non-selected by maintaining the word line WL at some constant voltage.
FIG. 2 is a circuit diagram for explaining the write circuitry associated with a conventional phase change memory device 200.
Referring to FIG. 2, the phase change memory device 200 includes a memory cell block CBLK, a word line driving unit 210, a column selection circuit 220, and a write driver 230. The memory cell block CBLK includes a plurality of phase change memory cells of the type illustrated in FIG. 1.
The column selection circuit 220 connects one of a plurality of bit lines BL0-BLk to the write driver 230 in accordance with a plurality of column selection signals Y0-Yk. The write driver 230 supplies a write current to the selected bit line
The word line driving unit 210 drives word lines WL0, WL1, and WL2 of the illustrated memory cell block CBLK. The word line driving unit 210 includes a plurality of word line driving circuits for decoding address signals ADD and activation signals EN. In the example of FIG. 2, each word line driving circuit WDC includes a NOR gate N1 and an inverter I1. As such, when both the applied address signal ADD and the applied activation signal EN are LOW, the corresponding word line WL is driven to ground VSS. If either or both the applied address signal ADD and the applied activation signal EN are HIGH, the corresponding word line WL is maintained at the voltage VDD.
The dashed line of FIG. 2 extending along the bit line BLk and the word line WL0 is representative of the current path in the case where the memory cell at the intersection of the bit line BLk and the word line WL0 is selected. As suggested previously, in this case, the word line WL0 is maintained at a ground voltage VSS by operation of the logic gates contained in the word line driving unit 210.
However, when the word line driving circuit connected to each of the word lines WL0, WL1, and WL2 includes logic gate circuits such as the NOR unit N1 and the inverter I1 shown in FIG. 2, the layout size of the word line driving circuit is increased, making it difficult to implement a highly integrated semiconductor memory device.